1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of testing a plurality of memory blocks in the semiconductor memory device and, more particularly, it relates to method of testing a plurality of memory blocks in a nonvolatile semiconductor memory device.
2. Description of the Related Art
In addition to a normal operation test performed by the unit of a memory cell in a semiconductor memory device, there is a stress applying test in which an electric stress is applied to all of the memory cells in order to secure their reliability.
In a nonvolatile semiconductor memory device, particularly, it is necessary to guarantee that the characteristics of programming or erasing of all of the memory cells and data retaining characteristics are normal. For example, there is a method to attain the above guarantee by applying an electric stress (an overvoltage or an overcurrent) to all of the memory cells for a certain period of time (stress applying time) in a stress applying test and comparing the characteristics before and after the test.
In the stress applying test, it is necessary to apply the stress to all of the memory cells (in which each terminal of the memory cell is set at a certain potential in order to apply the electric stress to the memory cell) for a certain period of time. A manufacturing cost (testing cost after manufacturing process, especially) can be lowered by applying the stress to the plurality of memory cells at the same time in order to shorten the total stress applying time in the stress applying test.
Meanwhile, there is a defective memory cell which does not operate normally because of a defect in s semiconductor substrate or particles generated during the manufacturing process in the semiconductor memory device. Therefore, if a perfectly good-quality product in which all memory cells operate normally is employed only, since the manufacturing yield is lowered, in general, there is a method of performing redundancy assist for the defective memory cell at the time of the test.
As redundancy assist technique in general, there is a method in which a defective row or a defective column containing a defective memory cell in a memory cell array, or a defective row or a defective column which is entirely defective is replaced with a redundant row or a redundant column, which are previously provided in the peripheral part of the memory cell array by the predetermined number. In this case, a defective row address and a defective column address are stored in defective address storing means and an address inputted from the outside is compared with stored defective row address and defective column address, and when they coincide with each other, the redundant row or the redundant column is automatically selected.
Although the above mentioned method is effective for a defective mode generated by the memory cell or along the row direction or the column direction, it is not so effective in a case many bits are continuously defective (in which the plurality of defective memory cells are continuously generated) caused by the particles, because the row or the column which can be assisted is limited by the number of the redundant rows or the redundant columns and the defects are frequently generated as the manufacturing process becomes fine.
Thus, there is a block redundancy assisting method in which a memory block consisting of a plurality of memory cells is assisted as one unit. According to this block redundancy assisting method, the case where many bits are continuously defective caused by the particles and the like can be effectively assisted and the manufacturing yield can be improved.
However, the defective cause of the defective memory block is not solved and the defective memory block is simply not used. Thus, when the stress applying test is performed for the assisted product, if there is a serious interconnect short-circuit problem as its cause, the electric stress is not normally applied because of the defective cause and the other normal memory block to which the electric stress is applied at the same time is not normally tested.
In addition, although there is a process for putting all of the memory cells in an erased state once at the time of testing in the nonvolatile semiconductor memory device such as a flash memory, the same problem occurs in the case all memory cells are erased at the same time. That is, there is a problem in which an erasing voltage level is lowered because of the interconnect short-circuit and the like when the erasing voltage is applied to the defective memory block, so that other normal memory blocks are not normally erased. In addition, when the voltage is applied to the plurality of memory blocks similarly, the same problem occurs if the defective memory blocks are contained in the plurality of memory blocks.
In order to solve the above problems, there is a method conventionally such that a predetermined electric stress is applied to all memory blocks which do not contain the defective block, and the electric stress is applied to each memory block which may contain the defective block without applying the voltage to all of the memory blocks at the same time.
In addition, a semiconductor memory device disclosed in JP-A 08-106796 (1996) has a constitution in which a defective block which is replaced with a redundant block is not selected when all memory blocks are in a batch programmed/erased mode for a test.
However, there is the following problem in the conventional stress applying test and the batch programming/erasing process for the memory blocks containing the defective block. That is, when the process is performed for each of the memory block containing the defective block, the processing time is increased by the number of the memory blocks, which causes the manufacturing cost to be increased. Particularly, since the number of memory blocks is increased because capacity is increased and the manufacturing process becomes fine, the number of memory blocks containing the defective memory block is increased, so that the manufacturing cost is further increased.
In addition, according to the above constitution of the semiconductor memory device disclosed in JP-A 08-106796 (1996), it is necessary to store an address of the defective block to identify the defective block in order not to select the defective block replaced with the redundant block and a test before the block redundancy assisting process or the stress applying test cannot be performed for it. In addition, the constitution disclosed in JP-A 08-106796 (1996) does not premise the defective block in the stress applying test particularly.